DSDV Lab Manual 2022 scheme VTU VTU University 1st SEM 1st SEM & 2nd SEM physics/Chemistry Cycle | BEC302 notes

Scheme & Syllabus Copy of DSDV Lab Manual 2022 scheme VTU

List of Experiments DSDV Lab Manual 2022 scheme VTU

1. Simplification of Boolean Expressions
   Simplify the given Boolean expressions and realize them using Verilog.

2. Adder/Subtractor Circuits
   Realize Full and Half Adder/Subtractor circuits using Verilog data flow description.

3. 4-Bit ALU
   Realize a 4-bit Arithmetic Logic Unit (ALU) using a Verilog program.

4. Code Converters
   Realize the following code converters using Verilog behavioral description:
   a) Gray to Binary and vice versa
   b) Binary to Excess-3 and vice versa

5. Multiplexers and Encoders
   Realize using Verilog behavioral description:

   • 8:1 Multiplexer
   • 8:3 Encoder
   • Priority Encoder

6. Demultiplexers and Decoders
   Realize using Verilog behavioral description:

   • 1:8 Demultiplexer
   • 3:8 Decoder
   • 2-bit Comparator

7. Flip-Flops
   Realize using Verilog behavioral description:

   • JK Flip-Flop
   • SR Flip-Flop
   • T Flip-Flop
   • D Flip-Flop

8. Counters
   Realize Up/Down Counters (BCD and Binary) using Verilog behavioral description.

Demonstration Experiments (For CIE Only - Not to be Included for SEE)

1. FPGA/CPLD Interfacing
   Use FPGA/CPLD kits for downloading Verilog codes and check the output for interfacing experiments.

2. Stepper Motor Interface
   Write a Verilog program to interface a stepper motor with the FPGA/CPLD and rotate the motor in the specified direction (by N steps).

3. Switches and LEDs Interface
   Write Verilog programs to interface switches and LEDs with the FPGA/CPLD and demonstrate their working.